Telecommunications systems have been an exception to the aforegoing for a relatively long time. In this case, the distances between communicating systems have been so great as to require synchronization already at moderate signal frequencies. Two methods have been applied chiefly in this regard:
1) Transmission of both a data signal and a clock signal from the source to the destination point, wherein the receiver receives the clock signal for interpreting the data signal. Adaptation to transmission delays for the clock and data signals must also be effected when interpreting data.
2) Recreation of the clock through an oscillating circuit or a phase-locked loop, with the aid of the so-called PLL technique. This requires the use of a line code.
After interpretation, it is also necessary in the majority of cases to transmit data to the time domain of the receiver system prior to further processing. This applies to both of the techniques given above. A double-port memory function is required for this purpose. In general, only a few signals require synchronization in these systems.
U.S. Pat. No. 4,181,975 teaches, for instance, a digital delay line apparatus for a case in which both clock signal and data signal are transmitted. The arrangement illustrates a technique of producing a digital continuous delay which replaces the incremental analogue delay elements normally used, these elements sometimes tending to introduce intermodulation between mutually adjacent signals when the signals to be delayed are digital data bits or pulses. This corresponds to the procedures mentioned under subparagraph 1) above.
U.S. Pat. No. 5,003,561 teaches another method of receiving a binary digital signal which may also contain a phase shift or jitter and with an accompanying clock signal which may have any desired phase position whatsoever in relation to the digital signal and may deviate slightly in frequency from the bit sequence frequency of the digital signal.
An example of restoring the clock in accordance with subparagraph 2) above is given for instance in U.S. Pat. No. 4,535,459. This example is effected with the aid of two bi-stable D-flip-flops and two exclusive OR-gates and a controlled oscillator of variable frequency. A corresponding system for an NRZ system is shown in U.S. Pat. No. 5,117,135.
Another example of digital phase alignment is given in U.S. Pat. No. 4,821,296. This example utilizes the advantage of the known synchronous bit speed of incoming signals and the fact that these signals are relatively pure, wherein data is sampled at two phases 0.degree. and 180.degree. of the local clock with the assumption that one of these two samples will contain correct data. A similar technique is described in a corresponding U.S. Pat. No. 4,756,011 having the same inventor, according to which samples are taken at phase angles 0.degree., 90.degree., 180.degree. and 270.degree. of the local clock. This technique is based on the use of a large number of registers to achieve phase alignment in a larger system with many incoming signals.
Innumerable high frequency data signals are used in many present-day systems, both in the actual system and for external communication. It is not possible to control propagation delays at the high degree of accuracy required to manage the system without synchronization. The majority of signals require synchronization in such systems and the methods defined in subparagraphs 1) and 2) above have certain drawbacks in this environment.
Method 1) of transmitting both clock and data signals duplicates the number of connections for each signal. The number of connections to a circuit or a circuit board has constituted a limiting construction factor for a long time. Duplication of the number of connections for a small number of signals can normally be accepted, although it cannot be achieved for the majority of the signals.
Oscillating circuits or PLL devices for method 2) require precision time control components which also consume the scarce availability of pins. The methods 1) and 2) both require a double port memory for each signal.
These weaknesses are overcome by the present invention. All data signals can be phase aligned with a common clock signal within the local time control domain and thus do not require a double port memory function.